1. Field of the Invention
The present invention relates to an automatic frequency correction PLL circuit provided with a voltage-controlled oscillator circuit (VCO) having the function of automatic oscillating frequency correction function which detects and automatically corrects an oscillating frequency deviation of this voltage-controlled oscillator circuit.
2. Background Art
In a phase-1ocked loop (PLL) circuit incorporating a voltage-controlled oscillator circuit, the oscillating frequency of the voltage-controlled oscillator circuit fluctuates due to variations in manufacturing processes, fluctuations in a supply voltage or ambient temperature during operation. To compensate for the fluctuations in this oscillating frequency, it is a general practice to set a wide range of the oscillating frequency beforehand. In this case, the ratio of fluctuation in the oscillating frequency to fluctuation in a control voltage of the voltage-controlled oscillator circuit, that is, VCO gain, is also set to a correspondingly large value.
When this VCO gain is large, when, for example, noise is applied to a node of the control voltage, the fluctuation in the oscillating frequency due to this noise also increases. This produces a timing shift called “jitter” in an output clock of the PLL circuit. In an on-chip PLL circuit which is a PLL circuit incorporating a voltage-controlled oscillator circuit formed on a semiconductor chip, the presence of large jitter in a clock causes the inconvenience of making it difficult to design synchronization of the entire semiconductor chip which constitutes the PLL circuit.
Prior art 1 for improving this noise sensitive characteristic is presented in a thesis titled “10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 μm digital CMOS process” by A. Ravi and five others at “2003 Symposium on VLSI Circuits Digest of Technical Papers” Session 14-2.
FIG. 10 is a block diagram of the PLL circuit shown in FIG. 16 of prior art 1 and FIG. 11 shows the structure of an internal capacitance section (capacitor) of the voltage-controlled oscillator circuit shown in FIG. 15. The PLL circuit of this prior art 1 carries out rough adjustment in a frequency correction of the voltage-controlled oscillator circuit VCO using bits of a digital control signal (Digital Control), Bit0, Bit1, Bit2, . . . through a digital control circuit including a digital frequency detector, state monitor circuit (State Machine) and counter & decoder during an initial operation, and then carries out fine adjustment in a frequency correction of the voltage-controlled oscillator circuit VCO using an analog control voltage (Vcntrl) through an analog control circuit including a phase frequency detector PFD, charge pump CP and loop filter.
However, the circuit of this prior art 1 has the following Problem 1 and Problem 2 which correspond to the following condition 1 and condition 2.
[Condition 1]
When an analog adjustment unit using the analog control circuit is equal to or smaller than a digital adjustment unit using the digital control circuit, that is, adjustment unit by the minimum capacitor 1C corresponding to the minimum bit bit0 of a digital control signal (Digital Control)
[Problem 1]
After an automatic correction by the digital control circuit, final frequency locking is performed using the analog control circuit. However, under this condition 1, the digital adjustment unit of the oscillating frequency using the digital control circuit is greater than the analog adjustment unit using the analog control circuit, and therefore the analog control voltage (Vcntrl) may be locked to an upper limit or lower limit of the analog adjustment range. In this case, after the locking of the oscillating frequency is completed, if the operating temperature or supply voltage fluctuates, there is a danger of the system becoming uncontrollable because the analog control voltage is set to the upper limit or lower limit.
[Condition 2]
When the analog adjustment unit of the oscillating frequency using the analog control circuit is greater than the digital adjustment unit using the digital control circuit,
[Problem 2]
Under this condition 2, the digital control circuit performs finer oscillating frequency adjustment than the analog control circuit. However, after the locking is completed, if the ambient temperature or supply voltage fluctuates producing a frequency error exceeding the digital adjustment unit using the digital control circuit, the digital control circuit responds to it, which may cause the oscillating frequency to change non-consecutively or discretely in response to the variation of the digital control signal (Digital Control).
Furthermore, as prior art 2, a thesis titled “A CMOS Self-Calibrating Frequency Synthesizer” by William B. Wilson and two others, issued in October 2000 and published in “IEEE JOURNAL OF SOLID-STATE CIRCUITS” VOL. 35, NO. 10, pp1437-1444 is also known. FIG. 12 is an automatic frequency correction PLL circuit shown in FIG. 9 of this thesis. In the circuit in this FIG. 12, it is possible to avoid the Problem 2 by connecting a control voltage of the voltage-controlled oscillator circuit VCO to Vref with a switch SWA set to OFF and switch SWB set to ON, thereby cutting the analog control circuit, adjusting the oscillating frequency through only a digital control signal (Digital Control) using the digital control circuit, and then fixing the digital control circuit so as not to operate, setting the switch SWA to ON and switch SWB to OFF to cause the PLL circuit to perform a normal operation.
However, prior art 2 also has another problem as shown below. That is, even the PLL circuit of prior art 2 cannot compensate the final potential of the locked analog control voltage (Vcntrl), and therefore the operation may be limited to between the upper limit or lower limit of the analog control voltage depending on the situation. Furthermore, according to prior art 2, once the setting is completed, the digital control circuit is fixed thereafter, and so after the locking of the PLL circuit is completed, even if the setting of the oscillating frequency by the digital control circuit becomes no longer optimal due to a variation in the operating environment such as ambient temperature or secular variation, etc., it is not possible to perform readjustment. According to the flow chart in FIG. 10 of prior art 2, this readjustment requires the power to be turned ON again.
Furthermore, as prior art 3, Japanese Patent Application Laid-Open No. 10-285023 is known. FIG. 13 shows the PLL circuit shown in FIG. 1 of prior art 3 in the same form as those of the prior arts in FIG. 10 and FIG. 12. The PLL circuit in FIG. 13 monitors an analog control voltage (Vcntrl), changes the offset frequency of the voltage-controlled oscillator circuit VCO to a higher value when the analog control voltage exceeds a High-side threshold VH and sets the analog control voltage (Vcntrl) to a value within the range. On the other hand, when the analog control voltage falls below a Low-side threshold VL, the PLL circuit changes the offset frequency to a lower value, and sets the analog control voltage (Vcntrl) to a value within the range.
In this prior art 3, the analog control voltage (Vcntrl) is monitored, and therefore there is an advantage that the control voltage of the voltage-controlled oscillator circuit VCO is compensated more reliably. However, another problem occurs as shown below. That is, since thresholds VH, VL are fixed, as shown with black bullets in FIG. 14, the frequency is also allowed to be locked to close to the high threshold VH as the initial state, and therefore once the frequency is locked, when the oscillating frequency characteristic changes with respect to the analog control voltage (Vcntrl) due to a variation of the external temperature, etc., the analog control voltage (Vcntrl) exceeds thresholds VH, VL and the changes indicated by arrows may occur. Thereafter, the stable state changes as indicated by a white bullet in FIG. 14, but the operation becomes unstable during an offset switching period. Therefore, even if the characteristic fluctuates during a relatively long period such as a variation in ambient temperature or secular variation, it is necessary to prevent offsets from being switched.
In FIG. 14, the vertical axis shows an oscillating frequency Freq.[Hz] of the voltage-controlled oscillator circuit VCO and the horizontal axis shows an analog control voltage (Vcntrl) and shows the control of the oscillating frequency Freq. Three thick straight lines show the control characteristic of the oscillating frequency Freq. by the analog control voltage (Vcntrl) and the thin straight lines above and below these three thick straight lines indicate the width of a characteristic fluctuation due to a temperature variation, etc., during operation.